1. Field of the Invention
The present invention generally relates to a method of fabricating capacitor plates applied to semiconductor devices. More particularly, the present invention relates to a method of fabricating stacked capacitors for application in dynamic random access memory devices.
2. Description of the Prior Art
High-performance capacitors are key elements for analog CMOS and BiCMOS technology, especially in the areas of A/D converters, D/A converters, oscillators, time-delay circuitry, and switched-capacitor filters. Moreover, capacitors are also important components for digital circuits, such as dynamic random-access-memory (DRAM) devices.
Essentially, a capacitor has two conducting plates (electrodes) spaced by an insulator. As well known by those persons skilled in this field, the most important parameters involved in affecting the charge stored on the capacitor are the dielectric constant and thickness of the insulator, and the area of the capacitor plates. However, as the DRAM cell has been scaled down in size, the minimum amount of stored charge needed to maintain reliable memory operation has remained the same. Therefore, a new technology is necessary allow the DRAM cell to shrink in size without a loss of its storage capacity.
It should be noted that a cell's storage capacity can be increased by making the capacitor dielectric thinner, by using an insulator with larger dielectric constant, or by increasing the area of the capacitor plates. The first two options are not currently feasible, since capacitor dielectrics thinner than those now being used in DRAM cells will suffer leakage due to Fowler-Nordheim tunneling, and insulators with significantly larger dielectric constants than that of silicon oxide have not yet been accepted for DRAM-cell application. The third approach, increasing the area of the capacitor plates, can be effective if the area is increased by forming the storage capacitor in three dimensions.
A stacked capacitor (STC) fabricated on top of the access transistor is one approach to increase the area of the capacitor plates, having features of low soft error rates and the capability of being combined with the application of high dielectric constant insulator.
However, since that the structure of three-dimensional stacked capacitors is quite complicated, the fabrication cost heavily dependent upon the number of masks will be used during photolithography processes. Yun's patent, U.S. Pat. No. 5,389,568, discloses a method of fabricating stacked capacitors, which makes use of two more masks to define bottom capacitor plates as shown in FIGS. 1 and 2.
Referring to FIG. 1, field oxides 101 are formed on a substrate 100 by means of thermal oxidation processes to define an active region therebetween. Transistors are fabricated on the substrate 100 within the active region. Reference numerals 45, 42, 44, 46 represent the source region, gate electrodes, drain region and bit line, respectively. An insulating layer 48 is deposited over the overall surface of the substrate 100 for isolation. A planarizing layer 50 and a conducting layer 52 are sequentially deposited on the insulating layer 48. Another insulating layer 54 is deposited on the conducting layer 52, and then patterned to form an opening just over the drain region 44 by means of a photolithography process.
Next, referring to FIG. 2, sequentially etching the insulating layer 54, the conducting layer 52, the planarizing layer 50, and the insulating layer 48 forms an opening 56 to expose the source regions 45 by means of another photolithography process. Thereafter, a doped polysilicon layer (not shown in FIG. 2) is conformably deposited over the substrate 100, electrically connected to the source regions 45 via the opening 56.
However, the addition of two masks increases the fabrication cost, so there is a need for a method of fabricating capacitor plates that can reduce the number of masks and thereby streamline the fabrication process.